Source

Tags: bspdn, powervia, super-power-rail, intel-18a, tsmc-a16, samsung-sf2z, hybrid-bonding, besi, amat, lrcx, asml, mlcc, murata, cpo, hbm4, foundry, ir-drop

• Source: The AI Power Crisis — Part 4
• Author: Nutty (@NuttyCLD)
• Date published: 2026-04-25
• Date captured: 2026-05-01

TL;DR

After grid → rack → board, the last stretch is inside the chip, measured in micrometers. Backside Power Delivery Network (BSPDN) flips the chip and feeds power from below — frees signal routing space, shortens the current path, cuts IR drop. Intel PowerVia in 18A is in production (Panther Lake, ramping 6-7x in Q2 2026). TSMC Super Power Rail in A16 pushed to 2027 ramp (was 2H 2026). Samsung SF2Z arrives 2027. Beneath BSPDN sits hybrid bonding — same toolkit family used for HBM stacking — making BESI and equipment majors (AMAT, LRCX, ASML) the picks-and-shovels winners. Adjacent layer ripples: GB300 uses ~30,000 MLCCs (13-15x traditional server); package capacitors (TSMC iCap/eDTC) move into the interposer; Co-Packaged Optics moves to AI fabric.

Key takeaways

• The arithmetic, fourth time: 1V chip × 1,500A B200, 2,300W → 2,875A Rubin. Tiny resistance becomes huge loss. Power and signals want different roads — power wants short/wide; signals want dense/complex. The frontside-shared network forces a tradeoff.
• BSPDN flips the chip: wafer is built normally, flipped, bonded to a carrier wafer,...